Synopsys CEO Sassine Ghazi and Nvidia CEO Jensen Huang recently took the stage at SNUG to discuss their collaboration and the incredible journey they have been on together. It turns out, Synopsys played a crucial role in helping Nvidia when they were just a startup, delivering much-needed simulation and design tools to ensure their chips were error-free.
The Silicon Complexity discussion between Jensen and Sassine highlighted the challenges that chip designers face in today’s complex landscape. The collaboration between Nvidia and Synopsys has yielded significant gains in productivity and performance, with AI-driven tools resulting in improved performance, power, and area, faster turn-around times, verification coverage, and more.
Synopsys has been pushing the boundaries of AI integration in their design and verification tools, with the introduction of DSO.AI and Synopsys.ai, their generative AI solution. They have also applied AI to 3D chip design, unveiling the Platform Architect – Multi-Die and 3DSO.ai tools to address thermal challenges and boost productivity.
The ZeBu EP2 emulation and prototyping platform was announced by Synopsys, capable of emulating chips up to 5.6B gates in size, a groundbreaking achievement in the industry. The company also launched the HAPS®-100 12 system, their highest capacity FPGA-based prototyping system, catering to the needs of multi-die systems and large SoCs.
Synopsys’ foray into hyperconvergence aims to optimize the EDA stack further by uncovering hidden PPA opportunities through AI integration. By automating rote engineering work and enhancing performance, power, and cost efficiencies in chip design, Synopsys is paving the way for a future where AI plays a significant role in the design process.
As we look towards the future of chip designing, it’s evident that technology is evolving rapidly, and companies like Synopsys are at the forefront of innovation. How do you see AI shaping the future of chip design? Share your thoughts and let us know in the comments below!
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